As semiconductor devices entering the 22 nm technique node, a horizontal channel 3D multi-gate device (MuGFET) represented by a fin-type field effect transistor (FinFET) becomes a main stream of semiconductor device due to the advantages of outstanding ability of suppressing short-channel effect, high integration density and compatibility with traditional CMOS processes, etc.
However, as scaled down to a smaller size technical node, the horizontal channel 3D multi-gate device faces the challenges that it is difficult to reduce the spacing of contact holes (which limits the increase of integration density) and gate etching is performed on a complex shape, etc.
By contrast, a vertical channel gate-all-around device gains much attention due to the advantages of higher integration density and a potential of hybrid integration with novel memories (for example, RRAM, etc.).
At present, a integration solution of a vertical nanowire device is mainly reported in Method For Forming A Channel Based On Etching, by B. Yang, et al., in EDL, 2008, 29 (7): 791˜794.
In this method, a vertical channel with a diameter of 20 nm and an aspect ratio greater than 50:1 is formed on a bulk silicon substrate by etching, and a source/drain of the device is formed by implantation, wherein a traditional SiO2 gate oxide and a polysilicon gate electrode are used.
However, when this method is employed to form a vertical nanowire channel device with a smaller size, the following problems will occur:
When a vertical channel with a smaller diameter and a large aspect ratio is formed by etching, a great challenge will be presented on the etching process, and it is difficult to control the cross-section shape of the channel formed by etching, thus the consistency of the device characteristics will be degraded; and channel damage caused by etching will further degrade the device performance;
An upper active region of the device formed by this method is a part of the vertical nanowire formed by etching, and the cross sectional area thereof decreases as the device size decreases, thus it is difficult to carry out heavy doping in this region by ion implantation, and the fluctuation of impurity concentration in this region between devices increases as the device size decreases;
It is difficult to employ a gate last process in this integration solution, which limits the improving of the device performance;
Therefore, there is an urgent need of an integration method of realizing a small-size vertical channel nanowire transistor in the industry.